As it is well known, level-shifter translators are circuits interfacing circuit logics with different supply voltages.
The technological development trend as regards circuitry of the digital type, such as for example transistors, logic gates or memory elements, is to decrease the supply voltages, thus forcing a reduction in the length of the channel interposed between source and drain in transistor-like structures. But in the case of non volatile memory, for example of the flash type, high supply voltages have not immediately undergone a reduction as in digital logic, and thus remain substantially unvaried.
Therefore, a need arises to interface circuit logics having more and more marked differences in the supply voltages. The difference between the supply voltage of a flash memory and the supply voltage of a memory cell transistor to be supplied continues to grow.
A first known technical solution to meet the need to interface circuit logics with marked differences in the supply voltage uses the circuit shown in FIG. 1.
This figure shows a standard shifter translator 1 with differential cell with positive feedback, comprising two pairs M1, M2 and M11, M12 of MOS transistors arranged symmetrically with respect to two reference terminals of supply VDD and ground GND voltages.
In particular, the transistor M1 of the NMOS type has a control terminal G1 to which is input a first supply signal Vin, for example of low logic value, has a conduction drain terminal coinciding with a circuit node B and a conduction source terminal coinciding with the ground terminal GND.
The transistor M2 of the NMOS type has in turn a control terminal G2 which is input a second supply signal corresponding to Vin, in this case a high logic value, has a conduction drain terminal coinciding with a circuit node A and a conduction source terminal coinciding with the source terminal of the transistor M1 thus connected to the ground terminal GND.
The transistor M2 has the drain terminal coinciding with a circuit node A and with a drain terminal of a transistor M12 of the PMOS type. The transistor M12 is, in turn, connected to the supply voltage VDD through its own source terminal. A control terminal G11 of a transistor M11 of the PMOS type is also connected to the circuit node A.
The transistor M11, of the PMOS type, symmetrical with respect to the transistor M12, has a source terminal connected to VDD and a drain terminal connected to a circuit node B, symmetrical with respect to the circuit node A, and connected to the drain terminal of the transistor M1. The circuit node B is also connected to the control terminal G12 of the transistor M12.
The voltage of the circuit node B is the output voltage Vout of the shifter translator 1.
Although advantageous in several aspects, this first known solution has various drawbacks.
For example, the transitions from the high logic level HV [high VDD] to the low logic level LV [GND], VDD=>GND, and vice versa from the low logic level to the high logic level, GND=>VDD, occur with very different times with respect to one another.
Moreover, the response times of the transitions VDD->GND and GND->VDD vary remarkably when the temperature varies.
The standard shifter translator 1, for its operation, resorts to a positive feedback which is started by varying the voltages at the nodes A and B in an opposite way. These nodes also respond to the commands at low voltage (LV), Vin and Vin, only if the transistors M1 and M2 of the NMOS type are much more conductive than the transistors M11 and M12 of the PMOS type, so as to “win” the positive feedback.
Additionally, once the positive feedback is started at the shifter circuit 1, a slowdown in the transaction from one level to the other may also occur due to the capacitive coupling which is created between the nodes A and B.
Thus, due to a more and more marked difference in the supply voltages of the logic and memory circuits, as above indicated, the transition from low to high voltage occurs with greater and greater difficulty. This implies that when logic circuits are interfaced, a delay is created which becomes a limiting factor for the performances of flash memory circuits, especially in terms of access time to the memory, where the times at stake are very narrow.